Field of the Invention
The present invention relates to a semiconductor integrated circuit wherein a given node is set at a predetermined potential level when the power source is turned on. For example, it relates to a CMOS (complementary insulated gate type) circuit which is incorporated in a semiconductor memory and in which a node connected to a nonvolatile memory cell is set at a predetermined potential level when information representing a defective address is stored in the nonvolatile memory of a redundancy circuit. When the phrase "to store information representing a defective address" is used herein, it refers to the act of storing information about a defective memory cell of a semiconductor memory into a redundancy circuit.
FIG. 1 shows a circuit which is incorporated in a conventional semiconductor memory and is used for setting data on a defective address in a redundancy circuit. In FIG. 1, "Vcc" denotes a power source potential, "Vss" denotes a ground potential, "31" denotes a polysilicon fuse, "32" and "33" denote capacitors, "34" and "35" denote CMOS inverters, "36" denotes a pull-up p-channel MOSFET (metal oxide semiconductor field effect transistor) which is cross-coupled to the CMOS inverter 34, and "37" denotes a resistor which forms a latch circuit 38 in cooperation with the pull-up transistor 36.
In the circuit shown in FIG. 1, the fuse 31 is blown in accordance with the one-bit data (namely, data "1" or "0") of a defective address of a redundancy circuit. The term "defective data (address)" is used herein to refer to the data representing that memory cell included in a semiconductor memory cell which becomes defective for some reason or other. When the fuse 31 is in an electrically-connected state, input node A of the latch circuit 38 is at the "L" (low) level. If the fuse 31 is blown and is therefore in an electrically-disconnected state, node A is pre-charged and set at the "H" level due to capacitive coupling, when the power source "Vcc" of the memory is turned on. Simultaneous with this, output node B is pre-charged and set at the "L" level. This state is maintained by the latch circuit 38 until the power source is turned off.
A circuit employing the above polysilicon fuse is disadvantageous, in that a laser-irradiating device or the like is required to blow the fuse 31 and in that one redundancy circuit cannot be switched to another after the chip of the memory is sealed within a package.
To eliminate these disadvantages, the redundancy circuit shown in FIG. 2 is proposed, which circuit employs a nonvolatile memory element constituted by an EPROM cell 41 (i.e., a read-only memory cell which is erasable and programmable upon irradiation of ultraviolet rays). As is shown in FIG. 2, the EPROM cell 41 is made up of a storage transistor 42 and a selection transistor 43. The storage transistor 42 is connected to a point set at a ground potential (Vss), while the selection transistor 43 is connected to input node A of a latch circuit 38 which is similar to that employed in the circuit shown in FIG. 1. In FIG. 2, like reference numerals and symbols represent like structural elements used in the circuit shown in FIG. 1.
In the circuit shown in FIG. 2, however, the parasitic capacitance of node A with reference to the ground potential (Vss) point is caused by the source and drain of the selection transistor 43 and by the drain of the storage transistor 42. Thus, the capacitance of node A is greater in the FIG. 2 circuit than in the FIG. 1 circuit. When the EPROM cell 41 is in the erased state (i.e., an ON state), node A is set in the "L" level without any problem. However, when the EPROM cell 41 is in the data-written state and its gate threshold voltage Vth is high (i.e., an OFF state), a great capacitance is required between node A and the power source potential (Vcc) point, in order for node A to be pre-charged into the "H" level. In the case of a 4M-bit EPROM, for example, 10 bits are necessary to record one address. If a memory incorporates eight redundancy circuits for low addresses, it is necessary to provide as large as 80 wide-area capacitors in correspondence to 80 EPROM cells. To provide so many wide-area capacitors is almost impossible in practice.
This problem may be solved by additionally employing a pulse-generating circuit which generates pulses when the power source is turned on and by permitting node A to be pre-charged by the pulse-generating circuit. An example of a circuit incorporating such a pulse-generating circuit is shown in FIG. 3. In the circuit shown in FIG. 3, a pre-charging p-channel MOS transistor 51 for precharging node A is connected between node A and a power source potential (Vcc) point. The gate of this pre-charging transistor 51 is supplied with an output of a pulse-generating circuit 52 when the power source is turned on. In FIG. 3, like reference numerals and symbols represent like structural elements used in the circuit shown in FIG. 2.
The fundamental operation of the FIG. 3 circuit is similar to that of the FIG. 2 circuit. When the power source is turned on, the pulse-generating circuit 52 shown in FIG. 3 operates as follows. The level of output node Q of a flip-flop 53 rises in such a manner that it follows the rise in the power source. A voltage at that level is applied to inverter 56 through two inverters 54 and 55. It is also applied to a delay circuit 57. After a certain time has elapsed, an n-channel transistor 58 is turned on, due to the output level of the delay circuit 57. As a result, node Q is returned to the "L" level. The flip-flop 53 maintains this state until the power source is turned off. Accordingly, a pulse which is kept at the "H" level during a short period of time is output from the inverter 55 when the power source is turned on.
The operation mentioned above is illustrated in the graphs shown FIGS. 4A and 4B. Where the power source rises in a short time, as is indicated in FIG. 4A, no problem occurs. However, where the power source does not rise in a short time or in a uniform manner, the pulse generation may be stopped before sufficient-voltage pulses are output from the inverter 55. Since the absolute value of the waveform amplitude at node Q corresponds to the source-gate voltage of the precharging p-channel transistor 51, it may happen in the worst case that the pulse generation will stop before the pre-charging transistor 51 is turned on. Needless to say, no problem occurs if the delay time provided by the delay circuit 57 is sufficiently longer than the rise time of the power source. However, the delay time cannot be lengthened without greatly increasing the pattern area. In addition, it is difficult, from the viewpoint of design, to determine the maximal value of the rise time of the power source.
As mentioned above, the conventional semiconductor integrated circuit has problems, in that if the power source does not rise quickly or uniformly, the generation of pulses stops before the pulses come to have a sufficiently high voltage, and in that a given node of the integrated circuit cannot therefore be set at a desirable potential level.